1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) and a method for fabricating the same, and more particularly, to a thin film transistor (TFT) liquid crystal display (LCD) and a method for fabricating the same.
2. Discussion of the Related Art
In order to reduce the power consumption of a TFT LCD, it is necessary to increase the aperture ratio of the TFT LCD. An aperture ratio of TFT LCD is defined as a ratio of the area in which display actually occurs to the entire area of the LCD panel. In most cases, a TFT LCD has a storage capacitor connected to the drain electrode of the TFT. The storage capacitor is typically constructed by an opaque film. Therefore, the area occupied by the storage capacitor is not used for display for a light-transmitting type LCD. Also, metal signal lines are typically formed of a non-transparent material. Thus, one way to increase the aperture ratio for LCD is to reduce the area occupied by the storage capacitor and/or the metal signal lines.
A method for fabricating a conventional TFT for a TFT LCD having a storage capacitor will be explained below with reference to FIGS. 1A to 1E. As shown in FIG. 1A, a semiconductor layer is deposited on a transparent insulating substrate 100, and patterned to form an active layer 1. Impurities are doped into a predetermined portion of the active layer 1 to form an impurity-doped semiconductor layer 2. Then, as shown in FIG. 1B, an insulating layer 5 is formed on the overall surface of the substrate 100 including the active layer 1 and the impurity-doped layer 2. A conductive layer, such as a doped polysilicon layer or a silicide layer, is formed on the insulating layer 5 and patterned to form a gate electrode 3 and a storage electrode 4. Impurities are ion-implanted into a portion of the active layer 1 to form source and drain regions, which are indicated by a new portion of the impurity-doped semiconductor layer 2 shown in FIG. 1C. Here, a portion of the insulating layer located below the gate electrode 3 serves as a gate insulating layer 5 for the TFT. The other portion of the insulating layer located below the storage electrode 4 serves as a dielectric layer 6 for a storage capacitor. In other words, the gate insulating layer 5 and the dielectric layer 6 are formed in the same step. Accordingly, they have the same thickness and dielectric constants.
As shown in FIG. 1D, an interlayer insulating layer 7 is formed on the overall surface of the substrate. The interlayer insulating layer 7 and the dielectric layer 6 and/or the gate insulating layer 5 are selectively etched to form contact holes exposing a portion of the impurity-doped semiconductor layer 2. Then, a conductive layer is formed on the overall surface of the substrate and patterned to form a source electrode 8 and a drain electrode 9, which are connected to the impurity-doped semiconductor layer 2 through the contact holes. As shown in FIG. 1E, a passivation layer 10 is formed on the overall surface of the substrate, and selectively etched to form a contact hole which exposes a portion of the drain electrode 9. Then, a transparent conductive layer is formed on the passivation layer 10 and patterned to form a pixel electrode 11. The pixel electrode 11 is connected to the drain electrode 9 through the contact hole, thereby completing a thin film transistor having a storage capacitor.
As described above, one way to increase the aperture ratio of TFT LCD is to reduce the area occupied by the storage capacitor. In order to reduce the area of the capacitor without sacrificing the capacitance, the dielectric layer 6 needs to be made thinner, or formed of a material having a dielectric constant larger. However, in the conventional method, since the gate insulating layer and dielectric layer are formed of the same layer, they have the same thickness and dielectric constants. Accordingly, only a limited adjustment of the thickness has been possible. Also, it has been impossible to form the dielectric layer 6 using a material having a dielectric constant larger than that of the gate insulating layer.